The ever-shrinking world of electronics has driven a constant stream of innovation in transistor design. From the planar MOSFETs of the past to the finFETs of today, researchers have tirelessly focused on improving device performance and overcoming the hurdles that arise when making transistors ever smaller. FinFETs, with their three-dimensional structure, have emerged as a game-changer, offering a path forward for the miniaturization trend at the heart of Moore’s Law.
This blog post delves into the intricacies of various finFET configurations, highlighting their key features and trade-offs. We’ll explore the fundamental difference between planar and 3D transistors, then delve into specific configurations like double-gate, tri-gate, and more.
Fig 1. Planar MOSFET
FinFETs conquer this challenge by introducing a third dimension. The transistor channel transforms from a flat plane into a thin fin, wrapped by a gate electrode.
Fig 2. FinFET
This 3D configuration offers several advantages:
Fig 3. Double-gate FinFET
Tri-Gate: A tri-gate FinFET boasts a single gate electrode wrapped around three sides of the fin. Unlike its double-gate counterpart, there’s no dielectric layer on top, allowing for full three-sided gate control. While offering advantages like reduced gate-source capacitance and increased effective transistor width, the additional gate adds complexity and introduces parasitic resistance.
Fig 4. Tri-gate FinFET
Choosing between double-gate and tri-gate configurations involves balancing factors like process complexity, gate control, and parasitic effects.
Fig 5. π-gate FinFET
Fig 6. Ω-gate FinFET
IG FinFET: In contrast, the IG FinFET offers independent control of the front and back gates, making it a four-terminal device. This essentially creates a double-gate structure with isolated gate electrodes, enabling separate biasing and individual channel control. One gate functions for switching, while the other modulates the threshold voltage. This configuration offers superior leakage current reduction but requires more area compared to the SG FinFET.
Fig 7. Independent-gate FinFET
The choice between SG and IG FinFETs hinges on the specific application requirements, with a trade-off between control and area consumption.
SOI FinFET: This configuration features an insulating layer (BOX or Buried Oxide layer) between the fin and the silicon substrate. Early research favored SOI substrates due to the ease of defining and controlling the fin shape using the oxide layer.
Fig 8. SOI FinFET
Bulk FinFET: Here, the fin connects directly to the bulk silicon substrate, eliminating the need for an SOI wafer. This approach, adopted by Intel in 2012, offers lower cost and better heat dissipation through the silicon substrate.
Fig 9. Bulk FinFET
Key Considerations:
Planar vs. Three-Dimensional (3D) FinFETs
Planar MOSFETs, the workhorses of the past, struggle with leakage current as their dimensions shrink.Fig 1. Planar MOSFET
FinFETs conquer this challenge by introducing a third dimension. The transistor channel transforms from a flat plane into a thin fin, wrapped by a gate electrode.
Fig 2. FinFET
This 3D configuration offers several advantages:
- Enhanced Gate Control: The gate surrounds the fin on two or more sides, exerting superior control over the channel electrostatics. This mitigates short-channel effects, a major hurdle in planar MOSFETs.
- Reduced Area Footprint: By utilizing the third dimension, FinFETs allow for a smaller transistor footprint while maintaining the same volume. This translates to more transistors packed into a chip, boosting integration density.
Double-Gate vs. Tri-Gate FinFETs
Double-Gate: As the name suggests, a double-gate FinFET has a single gate electrode facing two opposite sides of the fin (front and back). To prevent parasitic inversion channels at the top corners, a dielectric layer (hard mask) sits above the fin, restricting the electric field. Consequently, gate control is limited to the sides.Fig 3. Double-gate FinFET
Tri-Gate: A tri-gate FinFET boasts a single gate electrode wrapped around three sides of the fin. Unlike its double-gate counterpart, there’s no dielectric layer on top, allowing for full three-sided gate control. While offering advantages like reduced gate-source capacitance and increased effective transistor width, the additional gate adds complexity and introduces parasitic resistance.
Fig 4. Tri-gate FinFET
Choosing between double-gate and tri-gate configurations involves balancing factors like process complexity, gate control, and parasitic effects.
π-gate and Ω-gate FinFETs
These advanced FinFET configurations involve extending the sidewall sections of the traditional tri-gate FinFET beneath the channel, resembling the shapes of the Greek letters pi (π) and omega (Ω). This design effectively increases the number of effective gates from three to four, further improving electrostatic integrity.Fig 5. π-gate FinFET
Fig 6. Ω-gate FinFET
Shorted-Gate (SG) vs. Independent Gate (IG) FinFETs
SG FinFET: This configuration features the front and back gates short-circuited, resulting in a three-terminal device (source, drain, and gate). However, it lacks external control over the threshold voltage (Vth).IG FinFET: In contrast, the IG FinFET offers independent control of the front and back gates, making it a four-terminal device. This essentially creates a double-gate structure with isolated gate electrodes, enabling separate biasing and individual channel control. One gate functions for switching, while the other modulates the threshold voltage. This configuration offers superior leakage current reduction but requires more area compared to the SG FinFET.
Fig 7. Independent-gate FinFET
The choice between SG and IG FinFETs hinges on the specific application requirements, with a trade-off between control and area consumption.
Silicon-On-Insulator (SOI) vs. Bulk-Si FinFETs
FinFETs can be fabricated on either silicon-on-insulator (SOI) wafers or conventional bulk silicon wafers.SOI FinFET: This configuration features an insulating layer (BOX or Buried Oxide layer) between the fin and the silicon substrate. Early research favored SOI substrates due to the ease of defining and controlling the fin shape using the oxide layer.
Fig 8. SOI FinFET
Bulk FinFET: Here, the fin connects directly to the bulk silicon substrate, eliminating the need for an SOI wafer. This approach, adopted by Intel in 2012, offers lower cost and better heat dissipation through the silicon substrate.
Fig 9. Bulk FinFET
Key Considerations:
- SOI FinFETs is more expensive but offer lower heat dissipation and reduced parasitic capacitances.
- Bulk FinFETs are cheaper and provide better heat dissipation but introduce parasitic BJTs.