Thin film Process Engineer

Who are we?

Orbit & Skyline India Pvt. Ltd. is a leading semiconductor service provider with a robust and experienced team of professionals proficient in providing our customers with unique, feature-rich solutions that help them build environmentally friendly semiconductor manufacturing. At Orbit & Skyline, our synergistic cross functional team of Mechanical, Electrical, Electronics, Software, Equipment, and process engineering is delivering end to end solutions to our customers in semiconductor equipment manufacturing space. We are partnering with our customers across the complete semiconductor value chain spectrum that includes Hardware design and development, Supply chain management, Quality management, Product Management, Reliability, Data Science, ML/AI and many more. We are enabling our customers to develop technologies and systems that alter industries by employing one of the most diverse workforces of cutting-edge engineers and technologists in the semiconductor industry. Our clientele includes prestigious IC chip manufacturers and OEMs from the United States, Asia, the Middle East, and Europe with our services being rendered to our global customers out of our head office in Mohali, India. We have offices in the United States, the Middle East, Singapore, Taiwan, Ireland, and several other locations.

Who are we looking for?

• Bachelor's/Master’s/PhD in Electrical Engineering, Physics, Materials Science, or related field
• 3–10 years of experience in thin film deposition in HVM fabs preferable on SiC wafer

Strong understanding of:

• PECVD / CVD deposition mechanisms for high-temperature and wide bandgap substrates (SiC)
• Plasma-enhanced reactions involving TEOS, silane, oxygen, and nitrogen chemistries
• Film properties critical for SiC:
  • High-quality dielectrics (SiO₂, SiN)
  • Low interface trap density (Dit)
  • High breakdown strength
• Film stress engineering for thick oxides and passivation layers
• Step coverage challenges on trenches, mesas, and high-aspect-ratio structures

Hands-on experience with:

• Applied Materials (AMAT) P-TEOS PECVD systems (oxide deposition)
• SPTS Delta PECVD / CVD platforms (dielectric/passivation films)

Experience in:

• Film characterization:
  • Thickness & uniformity (Ellipsometry, XRR)
  • Refractive index and density
  • Film stress (wafer bow)
  • FTIR for bonding analysis (Si-O, Si-N)
  • Electrical characterization (leakage, breakdown)
• Interface quality evaluation (CV, Dit extraction)
• Deposition on SiC surfaces (epi, implanted, annealed surfaces)

Familiarity with:

• SPC, APC, and process control methodologies
• Data analysis tools (JMP, Python, MATLAB)
• Cleanroom contamination control (metal/particle sensitivity in dielectrics)

Roles And Responsibilities

• Exposure to high current / medium current / high energy implanters
• Develop and optimize dielectric deposition processes for SiC power devices (MOSFETs, diodes)
• Work extensively on:
  • AMAT P-TEOS oxide deposition (interlayer dielectrics, passivation)
  • SPTS Delta PECVD films (SiO₂, SiN, passivation layers)
• Define and optimize process parameters:
  • TEOS / silane / O₂ / N₂ / NH₃ gas chemistry
  • RF power tuning (HF/LF for plasma density and ion energy)
  • Pressure and temperature control
  • Deposition rate vs film quality trade-offs
• Engineer films for:
  • High breakdown voltage (>3 MV/cm typical for SiC devices)
  • Low interface trap density (Dit)
  • Controlled film stress (avoid cracking/peeling on SiC)
  • Excellent conformality on trench/edge structures
  • Perform advanced film characterization:
  • Electrical: leakage, breakdown, CV
  • Physical: thickness, uniformity, stress
  • Chemical: FTIR, composition
• Address SiC-specific challenges:
  • Poor native oxide quality vs Si
  • Interface defect states
  • Surface preparation sensitivity (pre-clean, plasma exposure)
  • Troubleshoot issues such as:
  • Film cracking or delamination (stress mismatch with SiC)
  • Non-uniform deposition across wafer
  • Plasma damage to SiC surface
  • Particle contamination affecting device yield
  • Collaborate with integration teams for:
  • Gate stack formation
  • Annealing and interface passivation (NO/N₂O anneals)
  • Etch compatibility and film integrity
• Drive:
  • SPC implementation
  • Yield improvement initiatives
  • Defect density reduction
  • Perform DOE, process window optimization, and statistical modeling
• Support:
  • Tool matching (AMAT ↔ SPTS platforms)
  • Qualification and production ramp-up

Why Orbit & Skyline?

Orbit & Skyline is an amalgamation of enthusiastic and experienced people working on a remarkable concept, making headway in this industry. Today, the Semiconductor Industry is going through a rapid transformation, and we are proud to be playing a major role in development of the semiconductor ecosystem in India thus providing our employees a platform to grow technically and introducing them to a versatile and sprouting work horizon. We offer a holistic workplace that encourages individuals to attain their full potential. We are a team of thinkers, planners, doers, and risk-takers who work closely together and enjoy the top-notch benefits such as:

• Safeguarding the health of our employees and their loved ones by providing them Health Insurance.
• Encouraging healthy, motivated and a happy workforce by providing monthly Wellness Allowances.
• Supporting effective and efficient communication by providing Communication Allowances.
• Awarding stability & loyalty of the employees by covering them under the Gratuity act.
• Providing technical advancements and interpersonal growth through periodic Trainings.
• Providing Service Award to celebrate employee’s contributions and show our gratitude for their loyalty and commitment.
• Rewarding and Recognizing employee’s efforts and contributions to the company’s growth.
• Encouraging enthusiasm, interaction, and motivation by organising team lunches, team outings, offsite activities, fun Fridays, festival celebrations, and other Engagement events.