SiC Seeding for Sustainable Green Energy: An Overview of SiC Crystal Growth and Wafer Processing

Silicon carbide (SiC) is gaining significant attention in the semiconductor industry due to its exceptional performance in high-power applications, such as electric vehicles, power grids, and renewable energy. Unlike traditional silicon, SiC offers superior efficiency in power devices, thanks to its wide bandgap, high electron mobility, and thermal conductivity.

This article provides an overview of SiC crystal growth and wafer processing techniques, highlighting the challenges and innovations in SiC production. With advancements in crystal growth, wafer slicing, and epitaxial growth, the semiconductor industry is making significant strides in making SiC a scalable, cost-effective solution for high-power applications.

1. Fundamentals of SiC Crystal Growth and Material Properties

1.1 SiC Requirements

Silicon carbide (SiC) is gaining significant attention in the semiconductor industry due to its wide range of applications, including electric vehicles, power grids, data centers, and renewable energy. With a bandgap three times wider and a significantly higher critical electric field (enabling higher breakdown voltage) compared to traditional silicon-based insulated-gate bipolar transistors (IGBTs), SiC excels in high-power applications. Additionally, its superior thermal conductivity allows for efficient heat dissipation under high-voltage operation, thereby reducing the need for costly cooling systems.

To meet the growing demand for high-performance SiC-based power devices, Orbit & Skyline offers specialized Semiconductor Fab Services, providing precision processing and advanced fabrication solutions engineered for SiC technology.

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1.2 SiC Crystal Structure

To develop highly efficient power-converting field-effect transistors, SiC wafers must meet specific prerequisites due to the material's crystal diversity, with over 250 polytypes, each exhibiting distinct electrical characteristics. Among these, the 4H, 6H, and 3C polytypes are favoured, particularly 4H crystal type is widely recognized for their advantageous properties, such as high electron mobility, high breakdown voltage and excellent thermal conductivity enabling SiC to effectively compete with the well-established silicon technology.

Want to understand why SiC is the future of high-power applications? Read our blog Silicon Carbide (SiC): The Future of the Compound Semiconductor Industry.

Unlike Si ingots, growing SiC single-crystal wafers at 6” and 8” scales are highly challenging due to the need for extremely high temperatures exceeding 2000°C, slow growth rates (0.5-2 mm/h), and the frequent occurrence of crystal defects such as micropipes, stacking faults, and high dislocation densities. However, the market is increasingly targeting 8” wafers, as their cost is comparable to 6” wafers while offering a higher device yield per wafer, ultimately reducing the overall cost per device.

1.3 SiC Boule Growth Methods

Among various growth techniques, the semiconductor industry primarily employs three major methods for growing single-crystal SiC boules, with the Physical Vapor Transport (PVT) method being the most widely adopted by SiC manufacturers. The PVT process relies on sublimation, as stoichiometric SiC does not coexist in the liquid phase. Due to the limited solubility of carbon in molten silicon, alternative methods are not commercially deployed for 4H crystal structure. Fig. 1.3 illustrates that the PVT method is suitable for high-power devices, offering higher scalability and production rates compared to the other two major growth technologies.

Given the complexity and challenges involved in growing SiC boules, Orbit & Skyline's Process Engineering expertise ensures higher yield and fewer defects by optimizing the growth processes. Through a well-structured engineering design process, we enhance crystal growth efficiency, scalability, and overall wafer quality.

Also, for a simplified breakdown of SiC's benefits and applications, visit our blog: Silicon Carbide (SiC): Properties, Benefits, and Applications.

1.4 Physical Vapor Transport

First, high-quality SiC powder is loaded into a furnace and melted at extremely high temperatures exceeding 2000°C. A high-quality SiC single-crystal seed is placed at the top of the chamber. In a controlled-pressure growth chamber, sublimated species like SiC₂, Si₂C, and atomic silicon undergo chemical reactions and deposit a single-crystal layer onto a high-quality seed crystal. Utilizing the PVT method, the vaporized SiC condenses onto the seed crystal, where the slightly lower temperature compared to the melt promotes crystallization. After the growth process, the boule is extracted for further processing. Single crystals seeds are then prepared from the grown boule by dicing and polishing it to the required specifications. Despite a high density of defects, n-type doped wafers have gained market traction due to their scalability and wide doping range with low activation energy. They also create carbon-rich regions during the sublimation process, promoting a stable 4H-crystal structure as carbon atoms substitute for carbon in the lattice to form n-type conductivity. In contrast, aluminium (a p-type dopant) favours the formation of the 6H polytype, which brings difficulty in controlling 4H crystal structure. Additionally, vanadium-incorporated growth (resistivity 10¹²–10¹⁵ Ω cm), high purity semi-insulating substrate (HPSI) with point defects (10¹² Ω cm) enable the production of semi-insulating substrates, which are critical for high-frequency 6G applications and transmission lines by preventing crosstalk.

The purity of SiC boules grown through sublimation is highly dependent on the purity of the SiC source material and the graphite components used in the process. Impurities, which vary among manufacturers, include elements such as Ti, V, Cr, Fe, Co, Ni, and S.

These unintended impurities can significantly impact the electrical properties and structural quality of the resulting SiC crystal. The color changes in SiC wafers occur due to differences in light absorption, which is influenced by the dopants and intrinsic defects altering the material's electronic structure. These color variations are useful for identifying the specific dopants and purity levels present in the SiC wafers [2].

2.0 Boule to Puck to Epi-ready Wafer Process

2.1 SiC Hardness and Challenges in Processing

SiC, ranked as the third hardest material with a 9–9.5 on the Mohs scale, is renowned for its high critical electric field strength, making it ideal for high-power electronic devices. However, its extreme hardness presents significant challenges during boule processing, particularly for dicing and wafer preparation. Once grown, the SiC boule typically has an irregular outer diameter (OD) that must be precisely shaped and sized for accurate wafer slicing. The process begins with centering and mounting the boule on a lathe or grinding system to align it with the crystal axis. Grinding, using diamond abrasives, removes surface irregularities and achieves a cylindrical shape. OD sizing further refines the diameter to meet strict tolerances, minimizing material waste during slicing. Surface finishing is then carried out to ensure a smooth and stress-free outer surface, enabling defect-free processing in subsequent stages.

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2.2 Wafer Slicing and Surface Preparation

After OD processing, the SiC boule undergoes slicing using advanced multi-wire saws equipped with diamond slurry-coated wire webs. These machines slice the boule into thin wafers, with precise control over wire speed, tension, and abrasive distribution to ensure minimal kerf loss, high throughput, and superior wafer quality. Following slicing, the wafers undergo lapping, a critical step to ensure flatness and uniform thickness. This process uses abrasive slurry and a rotating plate to balance material removal and surface finish, ensuring wafers meet the stringent requirements for further refinement. These steps are essential to prepare the wafers for the epitaxial growth process.

To ensure seamless equipment installation, calibration, and integration of equipment, visit our Tool Hook-Up Services page.

2.3 EPI-Ready Polishing and Innovations in SiC Wafering

The final stage of wafer preparation focuses on achieving EPI-ready quality through chemical mechanical polishing (CMP). CMP combines mechanical abrasion and chemical etching, using specially formulated slurries to remove surface defects and achieve an atomically smooth finish. This smooth surface is critical for defect-free epitaxial growth, as any irregularities can result in defects in the epitaxial layers, adversely affecting device performance, such as carrier mobility and breakdown voltage. While SiC CMP operates at slower material removal rates (MRR) compared to silicon, innovations like rapid thinning have revolutionized the process. By integrating advanced pad technology and diamond slurry, rapid thinning achieves higher MRRs (up to 1.5 μm/min) with surface roughness below 6 nm, reducing processing time and costs.

Together, these processes ensure that SiC wafers achieve the EPI-ready quality needed for high-performance, high-power, and high-temperature electronic applications.

Due to the hardness of SiC crystals, the processes involved are time-consuming. A single-stop solution is essential to enhance production rates, reduce manpower, and minimize costs. This solution should also address early-stage failures, as proper defect characterization tools at the boule level are lacking. While in-situ analysis aids in understanding crystal formation, many boule characteristics remain unexplored during growth. The BoulePro 200AX, a boule-to-puck conversion tool, utilizes X-ray and UV lamps to assess crystal quality and polytypes. On the other hand, alternative approaches, like those from Pureon AG, still require further exploration but promise a 40% cost reduction compared to conventional 8-step grinding and wafer thinning processes [2].
Most power device companies have developed proprietary technologies and in-house foundries to grow boules and convert them into wafers due to the high costs of consumables and low 
throughput in external supply chains. By self-supplying substrates, these companies can reduce the cost of the die by 25-40%.

3.0 Epitaxial Growth and Doping of SiC

Controlling the doping concentration during SiC boule growth remains a significant challenge. To address this, the development of homoepitaxy processes—where epitaxial layers are grown on a substrate of the same material in an orderly manner—plays a pivotal role in advancing SiC technology. Among various epitaxy methods such as Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), and sublimation epitaxy, High-Temperature Chemical Vapor Deposition (HT-CVD) is the most widely adopted technique in the industry due to its precision and scalability. 

Although CVD is the standard technique for SiC epitaxial growth, alternatives like LPE, sublimation epitaxy, and MBE have been explored. LPE allows homoepitaxy on 4H-SiC with growth rates of 5–30 μm/h but faces challenges with impurity incorporation, C/Si ratio control, and scalability due to the lack of stoichiometric SiC liquid phases. Sublimation epitaxy offers faster growth rates of 30–80 μm/h but struggles with background doping control and pn-junction formation. MBE enables atomic-level control and surface monitoring but is limited by its low growth rates of 0.05–0.2 μm/h and the challenges of high-temperature processing. HT-CVD, in contrast, enables precise control over critical SiC epitaxial parameters, such as doping concentration and layer thickness, making it indispensable for achieving the desired breakdown voltage and switching frequency in power devices.

The G10-SiC model from Aixtron facilitates the growth of high-quality SiC layers with precise control over layer thickness and doping concentration. It uses precursors like monosilane (SiH₄) and propane (C₃H₈) or ethylene (C₂H₄), diluted in carrier gases such as hydrogen (H₂) or argon (Ar). This tool supports uniform layer growth on substrates up to 8” in size. CVD growth typically occurs on the SiC (0001) plane under a controlled low C/Si ratio. Before growth, an in-situ cleaning process using HCl/H₂ is essential to prepare the substrate surface for high-quality epitaxy.

Summary

SiC wafer production is advancing with the transition from 6” to 8” wafers, addressing defects like threading edge dislocations (TED) and basal plane dislocations (BPD), which can reach densities of 10³–10⁴ cm⁻². Slicing processes with diamond-coated wire saws cut time from 16–20 hours to about 4 hours, improving efficiency while controlling thickness variation (TTV) to less than 2 µm. Single-side lapping enhances control but takes longer, with surface grinding completing in 5–10 minutes per wafer, reducing wafer loss to 1–2 wafers per batch compared to larger batch failures.

For 200 mm wafers, single-wafer grinders and polishers improve process throughput and control, overcoming batch limitations of just 3–4 wafers. Polishing steps benefit from pre-polishing with fine grinding wheels, reducing material removal needs. Cleaning lines process 20–50 wafers per hour, maintaining efficiency. Epitaxial growth thicknesses range from a few microns to over 50 µm, with doping profiles tailored for high-voltage devices (600–1,200 V), and growth times vary between 30 minutes to several hours per wafer. 

Expanding to 200 mm wafers increases device yields by 33% and enables retooling of older silicon fabs. SiC wafers, 50% thinner than silicon, demand equipment adaptations to minimize breakage. Boule growth at over 2,000°C, with energy consumption per boule exceeding several thousand kWh, underscores the push for renewable energy sources to enhance sustainability and reduce long-term production costs.

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